Author Topic: working of JK flip flop  (Read 648 times)

Amina Khatun

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working of JK flip flop
« on: July 04, 2013, 10:10:24 AM »
When J is low and K is high, the upper AND gate is disabled, so there is no way to set the flip flop. The only possibility is reset. When Q is high, the lower gate passes a reset pulse as soon as the next clock edge arrives. This forces Q to become low. Therefore, J=0, K=1 means that the next positive transition of the clock resets the flip flop.
The lower gate sends a reset pulse which means it sends a low voltage signal. Why does this happen? Now, the lower AND gate has 3 inputs. At the time the positive edge of clock pulse arrives, K=1. So, two of the inputs of the lower AND gate is high. Suppose at this instant, Q was high. Then three of the inputs of the lower AND gate is high, which means the output would be high .i.e. S is high. A high at any of the inputs of a NOR gate gives a low output. Hence Q is low. Now, Q is one of the inputs of the upper NOR gate. As J=0, R=0. Hence the two inputs of the upper NOR gate is low. Hence, Q=1.

Sanjoy Bachar

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Re: working of JK flip flop
« Reply #1 on: November 13, 2013, 12:31:43 AM »
thanks for sharing.
Sanjoy Bachar Sanju
BSc. & MSc. in Physics
Shahjalal University of Science & Technology,Sylhet
Instructor (Physics)
Bangladesh Skill Development Institute(BSDI)
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